Short Course/FDP
VLSI Testing

(26th April-28th April, 2019)

Recognized by AICTE at par with QIP for recognitions/credits

Venue: Indian Institute of Technology Roorkee

Certificates to participants by E&ICT Academy IIT Roorkee

Proficient candidates will get an opportunity to choose VLSI testing as a carrier in Qualcomm

Last Date for Registration: April 20th, 2019

Eligibility: Faculty/PhD/Research Scholars of engineering/technical institutions and persons from Govt. departments/labs and industry.

Experts from Academia/Industry: Dr. Ankush Srivastava (Qualcomm India Pvt.Ltd, Bengaluru), Dr. Anand Bulusu (IIT Roorkee)

Principal Investigator (E&ICT Academy IIT Roorkee): Dr. Sanjeev Manhas

Why VLSI Testing?

Today's IC design involves dealing with complex VLSI systems and increasingly large number of design constraints. Modern technology demands techniques for efficiently designing high- performance low-power integrated circuits while requirements for shorter time-to-market push down the design time. Apart from design cycle time reduction, these circuits demand technology scaling from planar to 3D FinFETs structure to improve transistor propagation delay and associated static/dynamic power. Technology scaling beyond 28nm node comes with a penalty of more number of localized physical defects in the silicon during manufacturing. Typically, such defects originate from spatial and temporal statistical variations in the circuit. This course will help the participants to understand, why such defects are growing concern in current FinFET and emerging gate all around (GAA) technologies. We will discuss and analyze the real silicon defects using scanning electron microscope (SEM) images, taken from commercial ICs.

Objective of the Course

  • To discuss and analyze the real silicon defects using scanning electron microscope (SEM) images, taken from commercial ICs.
  • Understand the techniques of modelling a defect into fault that can be used to generate test patterns.
  • Introduction of static timing analysis (STA) fundamentals like setup, hold, slack, arrival time, slack merging etc, with an aim to root- cause the underneath problem during circuit timing.
  • Benefits and Outcomes of the Course

  • The course will help participants to get acquaint to industry's state-of-the-art VLSI design flow, help researchers to foresee various research problems that can be pursued to fix practical testing problems and help faculty to adopt new techniques that must be included in their respective courses of basic electronics, VLSI design, CAD tools and digital integrated circuit design.

  • Course Program

  • The program is split into lectures and labs sessions.
  • Hands-on experience on basic & advanced-level topics.
  • Interaction & learning with experts from academia.
  • Certificates to the participants by E&ICT Academy IITR.
  • Recognized by AICTE at par with QIP for recognitions/credits.
  • E&ICT IITR learning material can be used while teaching presentation and projects.

  • Course Content:
  • Introduction to VLSI design flow and testing philosophy.
  • Silicon defects in commercial integrated circuits.
  • Translating silicon physical defects into fault models.
  • Design-for-test pattern generation and verification.
  • Small delay defects and timing critical paths.
  • Static timing analysis and its fundamentals.
  • Pits and falls in state-of-art STA techniques and proposed solution.
  • Digital design-for-test (DFT) and Scan design.
  • Basic of memory testing.
  • Save energy by allow errors in computing.

  • Important Details

    Last Date for Registration:
    April 20th, 2019
    40 seats on first-cum-first-serve basis
    3 days, 20 hours
    Food and Accommodation
    Free of cost inside the IITR campus. No travel allowance will be provided.
    Registration Fee
    Faculty Members/Research scholars: Rs. 1,000/-
    Persons from Industry: Rs. 1,500/-
    Payment mode (Read the instruction for payment)
    Offline: Demand draft drawn in favour of "Dean SRIC IIT Roorkee" payable at Roorkee
    Online: Click on the link (
    How to Apply
    You can apply online by click here to fill-up the application form OR you can download offline form and email scanned copy to
    Contact Details
    Dr. Sanjeev Manhas (P.I., E&ICT Academy, ECE Dept, IITR)
    Dr. Anand Bulusu (Co-PI, Local Co-ordinator, E&ICT Academy, ECE Dept, IITR),
    Tel: +91-7078627392, +91-1332-286457

    A hard copy of the application form along with Demand Draft must reach to the following address: Mr. Prateek Sharma, EICT Academy, ECE Department, IIT Roorkee, Uttarakhand 247667.

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